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Electrical Engineering
trayres's user avatar
trayres's user avatar
trayres's user avatar
trayres
  • Member for 12 years, 10 months
  • Last seen more than 1 year ago
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Senior Principle Digital Designer (FPGA) with deep hardware/software experience.

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Top posts
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16
ATMega8: why do VCC and AVCC have to be connected?
Oct 22, 2013
question
9
Cassette Input From TRS-80 - Design Review
Dec 9, 2012
question
4
inout port in VHDL RS232 Module from Digilent
Jan 1, 2013
question
4
Documenting Digital Design - Schematics and Figures
Jan 3, 2013
answer
4
Is it possible to build a inverter that operates at a frequency set by an LC tank using ONLY that LC tank and transistors?
Apr 4, 2012
question
3
Aldec Active-HDL - No Default Binding
Feb 13, 2013
question
2
pBlazSim Picoblaze simulator - Trouble Getting Started
Dec 26, 2012
question
2
Altium - having trouble pouring copper
Jul 10, 2013
question
1
Altium cannot find harness files of design
Jul 4, 2013
question
1
Configure Pin Swapping in Altium for a library component?
Jul 8, 2013
Top network posts
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111
Plot draws list of curves in same color when not using Evaluate
6
Add a comment to an array
6
"WindowsError: exception: access violation..." - ctypes question
5
Expected LP_c_double instance instead of c_double_Array - python ctypes error
5
MSYS2 inferior shell in Emacs on Windows