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Electrical Engineering
Martin Zabel's user avatar
Martin Zabel's user avatar
Martin Zabel's user avatar
Martin Zabel
  • Member for 8 years, 10 months
  • Last seen more than 2 years ago
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About

I'm a software engineer at MaibornWolff. Formerly, I was a teacher and research scientist at the Technische Universität Dresden, Germany. I'm also one of the authors of the PoC-Library on GitHub.

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Top posts
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question
9
Do I need to reset my FPGA design after startup?
Apr 12, 2016
answer
7
Xilinx ISE warns that a signal is trimmed since it has a constant value of 0, but the signal is used within my code
Apr 6, 2016
answer
6
VHDL simulation shows 'X' for input
Dec 30, 2015
answer
5
Why is D flip-flop positive edge triggered instead of level triggered?
Dec 12, 2015
answer
5
Xilinx clocking wizard - How to connect clkfb_in and clkfb_out
Dec 14, 2015
answer
4
Do I need to reset my FPGA design after startup?
Apr 14, 2016
answer
4
How to prevent from decreasing below 0 and Port Mapping
Nov 20, 2015
answer
4
shift register problem in VHDL
Mar 16, 2016
answer
3
VHDL error XST:1426
Nov 10, 2015
answer
3
Concatenation in port mapping
Nov 11, 2015
Top network posts
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13
copy data from kernel space to user space
13
wait statement must contain condition clause with UNTIL keyword
12
Unable to write on /dev/* files
8
Calculating the Overflow Flag in an ALU
6
x86 Intel Assembly and C++ - Stack around array corrupted