Electrical Engineering
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drdot
  • Member for 11 years, 5 months
  • Last seen more than a month ago
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2
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16
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39
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7
Posts
39
Posts %
0
Score
4
Posts
22
Posts %
0
Score
4
Posts
22
Posts %
0
Score
4
Posts
22
Posts %
Top posts
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All Questions Answers
Score Newest
question
6
Verilog Netlist format with "\"
Apr 3, 2013
question
6
Oscilloscope noise reduction when measuring IC voltage
Apr 26, 2013
question
3
Oscilloscope acquisition frequency
Jun 26, 2012
question
3
Static power of Xilinx FPGA
Apr 18, 2013
question
2
constraint error and illegal load problem in Virtex-2
Jun 21, 2012
question
2
RTL compiler timing constraint error
Apr 5, 2013
question
2
Oscillocope interleave mode and repetitive mode
May 13, 2013
answer
2
RTL compiler timing constraint error
Apr 15, 2013
question
1
RS232 output always follow with an extra 0x0b
Jun 16, 2012
question
1
Estimating power consumption in cadence RTL compiler with VCD file
Mar 28, 2013
Top network posts
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33
Why does Chrome send four browsers in the user-agent header?
20
Get the enum value out from protobuf messages
18
What is the difference between system call and library call?
13
How to send UDP packet to specific UDP dst port in scapy?
12
Constant definition in multiple files

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