Electrical Engineering
Zane Kaminski
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11 Good uses for 1:1 probe Dec 7 '17
9 "recommended that CLK begin toggling within 150 ms ... to ensure long-term reliability of the device" -- why? Dec 13 '19
7 How can I avoid a clock glitch? Dec 18 '20
6 PCB layout: am I doing local power nets correctly? Aug 2 '16
6 ARM Cortex-M4 VFMA (fused multiply-add) performance? 3, 2 or 1 clock? Forwarding? Jan 26
5 For decoupling an IC's power supply pins, is there any reason to use multiple capacitances when all the MLCCs have the same package size? Jun 25 '19
4 Do manufacturers try make their components as close to ideal ones as possible? Jun 1 '19
3 What logic family is best for general-purpose hobbyist stuff? Dec 10 '17
3 Phase-locking pixel clock to HSYNC/VSYNC Jan 15 '17
2 ~40 uA current sink... what current mirror topology to use? Jun 11 '18
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