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koalag

6502 assembly enthusiast

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  • Dresden, Germany
  • Member for 4 years, 7 months
  • 43 profile views
  • Last seen Jun 30 at 8:09

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2 Work library is empty after compiling Verilog source file in Modelsim Feb 20 '18
2 VHDL: Declaring an empty array (in a test bench) Feb 21 '18
2 VHDL: Metastability check for hold time fails Sep 23 '18
2 How do I learn-by-practicing digital circuits - MIPS R2000 (or similar) processor or board? Oct 15 '18
1 VHDL: Real addition leads to 'bound check failure' Feb 18 '18
1 Number of electron with a current of 1A Mar 21 '18
1 Design on ALU in multisim Feb 27 '18
1 Problem with glue logic/memory decoding on a 6502 project Dec 1 '15
1 Faulty display behavior using a Atmega328 due to (wrong?) logic voltage level Jun 21 '16
1 Compiling a simple 2-input multiplexer with GHDL fails Aug 20 '16
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