Skip to main content
Electrical Engineering
HWDesigner's user avatar
HWDesigner's user avatar
HWDesigner's user avatar
HWDesigner
  • Member for 8 years, 10 months
  • Last seen more than a month ago
  • San Jose, CA, United States
Profile Activity
Stats
147
reputation
42k
reached
0
answers
16
questions
Communities
View all
About

A motivated and result-driven Electronics Engineer.

Badges
View all badges
1
gold badge
5
silver badges
20
bronze badges
Top tags
View all tags
0
Score
9
Posts
56
Posts %
0
Score
5
Posts
31
Posts %
0
Score
4
Posts
25
Posts %
0
Score
2
Posts
12
Posts %
0
Score
2
Posts
12
Posts %
0
Score
2
Posts
12
Posts %
Top posts
View all questions and answers
question
3
Is it good to code combinational and sequential logic separated into two always blocks?
Nov 18, 2016
question
3
What is the critical path in the design?
Nov 30, 2016
question
1
What does the GSM AT+CSQ command output signify?
Feb 5, 2016
question
1
Is it possible to implement a fail-proof watchdog timer in software?
Feb 6, 2016
question
1
Why do we use negative edge trigger Flip Flop instead of positive edge triggered?
Oct 29, 2016
question
1
What is the relation between noise margin and impedance in a CMOS circuit?
Nov 16, 2016
question
1
Why is de-assertion of an asychronous reset a problem compared to its assertion?
Dec 20, 2016
question
1
What is the need for implementing synthesizable linked list module in RTL?
Apr 7
question
0
Why asynchronous counters can not work at high clock frequencies?
Oct 30, 2016
question
0
How does the clock skew affect the design?
Oct 30, 2016