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user3219492's user avatar
user3219492's user avatar
user3219492
  • Member for 8 years, 7 months
  • Last seen more than 1 year ago
8 votes
Accepted

How is the input not floating when there is a pull-down resistor?

7 votes
Accepted

Y to Delta transform with inductors?

4 votes
Accepted

Why voltage source is not included while using KVL?

3 votes
Accepted

Current flow in a BJT transistor

3 votes
Accepted

Understanding the guarding circuit in an instrumentation amplifier

3 votes
Accepted

How to find the resistor using the equivalent resistance?

2 votes
Accepted

sample input signals and check their values VHDL

2 votes
Accepted

Is it wrong to assume the op-amp has the same voltage at its both terminals when deriving its non-inverting closed-loop gain?

2 votes

How to differ output & input resistance of small-signal model BJT?

1 vote

Issue with Booth multiplier

1 vote

Unit of permitivity

1 vote

Problem about the properties of convolution

1 vote

Need help understanding this PWM Generator

1 vote

How to calculate time constant for RC circuit with more than one resistor

1 vote
Accepted

Does current fundamentally determine the speed or the quantity of electrons in a curcit?

1 vote

Given the system function, how can i tell if it is a lowpass or a highpass filter?

1 vote
Accepted

NPN transistor circuit confusion

1 vote
Accepted

Proof of formula to convert from parallel to series impedance

0 votes

Transient analysis with current source

0 votes

Heating up water with electrical current

0 votes
Accepted

Why a transistor (MOS) changes the output current (Ids) with changes of a load resistor?

0 votes

Twin T active notch filter

0 votes

MATLAB: Pole at 0.1 rad/s contributing to nothing on the Bode Plot - Why?

0 votes

Output resistance of non-inverting amplifier

0 votes

Order of the filter

0 votes

How does feedback make a system stable even in the presence of an inherently unstable element in that?

0 votes

Phase between two sinusoids and which one is leading

0 votes

Design an op amp with gain of \$2\cdot V1+4\cdot V2-2\cdot V3-4\cdot V4\$

0 votes
Accepted

Why the simulation time of a synthesized netlist depends on the clock period at which it is constrained?

0 votes

Optoisolator circuit using IL300