Timeline for Reading a multibyte volatile variable that is updated in an ISR
Current License: CC BY-SA 3.0
10 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Mar 21, 2014 at 7:41 | vote | accept | jippie | ||
| Mar 12, 2014 at 21:55 | history | edited | jippie | CC BY-SA 3.0 |
added 1 characters in body
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| Mar 12, 2014 at 21:36 | history | edited | jippie | CC BY-SA 3.0 |
added 148 characters in body
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| Mar 12, 2014 at 21:30 | answer | added | JRobert | timeline score: 0 | |
| Mar 12, 2014 at 21:22 | history | edited | jippie | CC BY-SA 3.0 |
added 96 characters in body
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| Mar 12, 2014 at 20:52 | answer | added | markrages | timeline score: 2 | |
| Mar 12, 2014 at 20:39 | answer | added | Dave Tweed | timeline score: 2 | |
| Mar 12, 2014 at 20:38 | comment | added | Martin | tmp needs to be volatile to prevent it being optimised out. | |
| Mar 12, 2014 at 20:34 | comment | added | alexan_e | I think the intermediate variable is the best way to avoid the problem (unless you can get away with an 8bit variable or do the check inside the interrupt), that is probably why this way is shown as an example in the atomic library | |
| Mar 12, 2014 at 19:55 | history | asked | jippie | CC BY-SA 3.0 |