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Timeline for Counter is missing an output signal

Current License: CC BY-SA 3.0

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Jan 27, 2015 at 17:27 answer added Peter Cormack timeline score: 0
Jun 20, 2014 at 17:13 answer added WhatRoughBeast timeline score: 0
Jun 20, 2014 at 15:53 comment added Mark0923 but if for this case, for RC delate how should be value for resistor and Capacitor is better?
Jun 20, 2014 at 15:51 comment added Peter Bennett Although I don't think it is a problem, you should use a 74HC08, rather than the HCT - the HCT family has lower input thresholds to properly accept bipolar TTL signals. Also, I don't see any reason for the series resistors you have on the 74HCT08 inputs.
Jun 20, 2014 at 14:59 history edited W5VO CC BY-SA 3.0
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Jun 20, 2014 at 13:29 vote accept Mark0923
Jun 20, 2014 at 13:29
Jun 20, 2014 at 10:34 comment added James Cameron But you are connecting to the master reset pin. Your multimeter is too slow. The master reset pin is much faster. I agree with Andy aka.
Jun 20, 2014 at 10:29 answer added Andy aka timeline score: 6
Jun 20, 2014 at 9:52 comment added Mark0923 @JamesCameron yes, the problem is like, no matter which output i use from Texas Instruments 4040 counter, once i connect to the logic gate, it will have no out put signal, but if i disconnect that, all the signal will come back again...this is why i feel confused. my colleague said maybe because of the logic gate has a too high impedance,is it possible?
Jun 20, 2014 at 9:39 comment added James Cameron @fmunkert, yes, I noticed, the datasheet numbers from Q0, but the schematic here numbers from Q1. Mark0923, you say that with Q9 tied to master reset alone you have a problem, but I'm not sure what the problem is. You should see low output on Q9 all the time, and you would need oscilloscope or other instrument to see very brief high output on Q9. Q8 will show a signal. Q10 will not.
Jun 20, 2014 at 9:35 comment added Mark0923 @JamesCameron Thank you for your reply, i disconnect IC1D totally,that means i only use Q9 goes to IC5 directly(although the counting number will become lower,but not so big difference),and i measured at Pin 12(Q9)(see the second one),but still has that problem.
Jun 20, 2014 at 9:34 history edited Mark0923 CC BY-SA 3.0
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Jun 20, 2014 at 9:32 review First posts
Jun 20, 2014 at 10:16
Jun 20, 2014 at 9:29 comment added user36113 According to NXP's 4040 datasheet, Q7 and Q9 are on pins 13 and 14, respectively. It is different on your circuit diagram. (But doesn't explain the problem you observe).
Jun 20, 2014 at 9:22 comment added James Cameron I have reviewed 4040 datasheet. I have reviewed your schematic. It looks fine; the counter will increment until Q7 and Q9 are both high, then the master reset will be raised momentarily and this will reset the counter and force Q7 and Q9 low. I ask for more information: what were IC1D pins 13 and 12 connected to when R9 and R10 were removed? Can you edit the question to clearly show the two test configurations, and where you made measurements? That part of the question is confusing.
Jun 20, 2014 at 9:15 history asked Mark0923 CC BY-SA 3.0