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Datasheet covers this:

RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level

So you don't lose buffer values but any operation in progress is stopped and the state machine is reset. So the data in the buffer is invalid (does not line up with current state and may not line up with whats actually in flash, it should be treated as garbage).

If you trip the software reset while a write or read from flash is occurring the operation stops and upon release of the software reset the shipchip is in its default state. This means that the software reset can corrupt flash data without changing the buffer values. When you write to the flash you have to make sure you allow enough time for the chip to actually write the data to the flash before using the software reset or your data will be not make it to the flash. These times are listed in section 8.2 of the datasheet.

Strictly speaking it is also not safe to read from the data buffer as if it were valid after a software reset, you must re-issue a command to copy data from flash to the buffer before you can read it and be assured that it is valid (equivalent to whats actually in flash).

Additionally:

The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally

and

When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a highto-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. After power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started

So there is no need for an external controller to bring the chip online on power up. Unless your power on operation takes more than 20ms to stabilize supply voltage you shouldn't have any power on garbage issues.

Datasheet covers this:

RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level

So you don't lose buffer values but any operation in progress is stopped and the state machine is reset. So the data in the buffer is invalid (does not line up with current state and may not line up with whats actually in flash, it should be treated as garbage).

If you trip the software reset while a write or read from flash is occurring the operation stops and upon release of the software reset the ship is in its default state. This means that the software reset can corrupt flash data without changing the buffer values. When you write to the flash you have to make sure you allow enough time for the chip to actually write the data to the flash before using the software reset or your data will be not make it to the flash. These times are listed in section 8.2 of the datasheet.

Additionally:

The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally

and

When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a highto-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. After power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started

So there is no need for an external controller to bring the chip online on power up. Unless your power on operation takes more than 20ms to stabilize supply voltage you shouldn't have any power on garbage issues.

Datasheet covers this:

RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level

So you don't lose buffer values but any operation in progress is stopped and the state machine is reset. So the data in the buffer is invalid (does not line up with current state and may not line up with whats actually in flash, it should be treated as garbage).

If you trip the software reset while a write or read from flash is occurring the operation stops and upon release of the software reset the chip is in its default state. This means that the software reset can corrupt flash data without changing the buffer values. When you write to the flash you have to make sure you allow enough time for the chip to actually write the data to the flash before using the software reset or your data will be not make it to the flash. These times are listed in section 8.2 of the datasheet.

Strictly speaking it is also not safe to read from the data buffer as if it were valid after a software reset, you must re-issue a command to copy data from flash to the buffer before you can read it and be assured that it is valid (equivalent to whats actually in flash).

Additionally:

The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally

and

When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a highto-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. After power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started

So there is no need for an external controller to bring the chip online on power up. Unless your power on operation takes more than 20ms to stabilize supply voltage you shouldn't have any power on garbage issues.

Source Link
Mark
Mark
  • 11.7k
  • 1
  • 33
  • 38

Datasheet covers this:

RESET: A low state on the reset pin (RESET) will terminate the operation in progress and reset the internal state machine to an idle state. The device will remain in the reset condition as long as a low level is present on the RESET pin. Normal operation can resume once the RESET pin is brought back to a high level

So you don't lose buffer values but any operation in progress is stopped and the state machine is reset. So the data in the buffer is invalid (does not line up with current state and may not line up with whats actually in flash, it should be treated as garbage).

If you trip the software reset while a write or read from flash is occurring the operation stops and upon release of the software reset the ship is in its default state. This means that the software reset can corrupt flash data without changing the buffer values. When you write to the flash you have to make sure you allow enough time for the chip to actually write the data to the flash before using the software reset or your data will be not make it to the flash. These times are listed in section 8.2 of the datasheet.

Additionally:

The device incorporates an internal power-on reset circuit, so there are no restrictions on the RESET pin during power-on sequences. If this pin and feature are not utilized it is recommended that the RESET pin be driven high externally

and

When power is first applied to the device, or when recovering from a reset condition, the device will default to SPI Mode 3. In addition, the SO pin will be in a high-impedance state, and a highto-low transition on the CS pin will be required to start a valid instruction. The SPI mode will be automatically selected on every falling edge of CS by sampling the inactive clock state. After power is applied and VCC is at the minimum datasheet value, the system should wait 20 ms before an operational mode is started

So there is no need for an external controller to bring the chip online on power up. Unless your power on operation takes more than 20ms to stabilize supply voltage you shouldn't have any power on garbage issues.