Timeline for Reducing the memory address bus by adding banks
Current License: CC BY-SA 2.5
6 events
| when toggle format | what | by | license | comment | |
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| Mar 23, 2011 at 9:36 | comment | added | W5VO | If you want to switch chips every read, then you can use the LSB as CS. You can even use a combination of MSB and LSB or any bits in the address, and it will still work. If you are trying to interleave your chips to get a performance advantage, your system must be able to take advantage of that. | |
| Mar 23, 2011 at 9:22 | comment | added | 200ok404notfound | If you look at page 13 on here the LSB is being used. ece.cmu.edu/~ece548/handouts/13m_arch.pdf | |
| Mar 23, 2011 at 9:14 | history | edited | W5VO | CC BY-SA 2.5 |
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| Mar 23, 2011 at 9:09 | comment | added | W5VO | No, you use the MSB's. That way you're not switching chips every time you increment the address. This makes it much easier to use ROM chips, partially filled address spaces, and devices with a memory bus interface. | |
| Mar 23, 2011 at 4:02 | comment | added | 200ok404notfound | Don't you mean that the LSB is used for the chip select? | |
| Mar 22, 2011 at 3:01 | history | answered | W5VO | CC BY-SA 2.5 |