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I am afraid that the term "MILLER" capacitance has not yet been properly explained. It was said that the MILLER capacitance would be identical to the drain-to-gate capacitance. I think, this neeeds clarification.

The problem is that the MILLER effect (caused by negative feedback) increases the input conductance at the gate (in case of common source configurations). This applies to any conducting element between drain and gate (inside and/or outside the device).

Roughly we can say that the MILLER effect apparently increases the input capacitance at the gate by a factor equal to the gain A of the stage, hence: Cin~A*Cdg.

That means - as far as modeling is concerned: The MILLER effect is not modeled at all and Cdg is modeled as it is (between D and G). A possible increase due to the MILLER effect depends on the particular application.

I am afraid that the term "Miller" capacitance has not yet been properly explained. It was said that the Miller capacitance would be identical to the drain-to-gate capacitance. I think, this neeeds clarification.

The problem is that the Miller effect (caused by negative feedback) increases the input conductance at the gate (in case of common source configurations). This applies to any conducting element between drain and gate (inside and/or outside the device).

Roughly we can say that the Miller effect apparently increases the input capacitance at the gate by a factor equal to the gain A of the stage, hence: Cin~A*Cdg.

That means - as far as modeling is concerned: The Miller effect is not modeled at all and Cdg is modeled as it is (between D and G). A possible increase due to the Miller effect depends on the particular application.

I am afraid that the term "MILLER" capacitance has not yet been properly explained. It was said that the MILLER capacitance would be identical to the drain-to-gate capacitance. I think, this neeeds clarification.

The problem is that the MILLER effect (caused by negative feedback) increases the input conductance at the gate (in case of common source configurations). This applies to any conducting element between drain and gate (inside and/or outside) the device.

Roughly we can say that the MILLER effect apparently increases the input capacitance at the gate by a factor equal to the gain A of the stage, hence: Cin~A*Cdg.

That means - as far as modeling is concerned: The MILLER effect is not modeled at all and Cdg is modeled as it is (between D and G). A possible increase due to the MILLER effect depends on the particular application.

I am afraid that the term "MILLER" capacitance has not yet been properly explained. It was said that the MILLER capacitance would be identical to the drain-to-gate capacitance. I think, this neeeds clarification.

The problem is that the MILLER effect (caused by negative feedback) increases the input conductance at the gate (in case of common source configurations). This applies to any conducting element between drain and gate (inside and/or outside the device).

Roughly we can say that the MILLER effect apparently increases the input capacitance at the gate by a factor equal to the gain A of the stage, hence: Cin~A*Cdg.

That means - as far as modeling is concerned: The MILLER effect is not modeled at all and Cdg is modeled as it is (between D and G). A possible increase due to the MILLER effect depends on the particular application.

I am afraid that the term "MILLER" capacitance has not yet been properly explained. It was said that the MILLER capacitance would be identical to the drain-to-gate capacitance. I think, this neeeds clarification.

The problem is that the MILLER effect (caused by negative feedback) increases the input conductance at the gate (in case of common source configurations). This applies to any conducting element between drain and gate (inside and/or outside) the device.

Roughly we can say that the MILLER effect apparently increases the input capacitance at the gate by a factor equal to the gain A of the stage, hence: Cin~A*Cdg.

That means - as far as modeling is concerned: Cdg is modeled as it is (between D and G) and a possible increase due to the MILLER effect depends on the particular application.

I am afraid that the term "MILLER" capacitance has not yet been properly explained. It was said that the MILLER capacitance would be identical to the drain-to-gate capacitance. I think, this neeeds clarification.

The problem is that the MILLER effect (caused by negative feedback) increases the input conductance at the gate (in case of common source configurations). This applies to any conducting element between drain and gate (inside and/or outside) the device.

Roughly we can say that the MILLER effect apparently increases the input capacitance at the gate by a factor equal to the gain A of the stage, hence: Cin~A*Cdg.

That means - as far as modeling is concerned: The MILLER effect is not modeled at all and Cdg is modeled as it is (between D and G). A possible increase due to the MILLER effect depends on the particular application.