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Where memory elements such as latches and flip-flops are involved, the terms clocking and latching describe what is the sensitivity of the memory element to the control signal, which is often labeled "Clock". In this context, "Clocking" means an edge-sensitive operation and "Latching" means a level-sensitive operation.

The most basic memory element is a form of positive feedback loop called a "Latch". One such element can be formed for example by cross-wiring two NAND gates so that the output of one holds the state of the other, and vice versa. It can be extended to become something called "D-Latch", which has a Data input and a Latch Enable input. Sometimes it's called a "D-follower", because for as long as the Latch Enable input is high, the output of the circuit "follows" the input of the circuit. But when the Latch Enable drops low, the output remains fixed - whatever was in the inputs when the Latch Enable drops from high to low, is "latched" into the element.

Now, consider that you would make another latch and invert its Latch Enable signal. You'd then have another latch which scans its inputs when the Latch Enable is low and holds its output when the Latch Enable is high. Understandable enough, right?

Finally, see what happens if you place this second latch "in front" of the first latch, so that he the output of the "active low" latch goes to the input of the "active high" latch. Connect the Latch Enable signals together. What you have formed is something that was originally called a "Master-Slave Latch" and quickly renamed to master-slave "Flip-Flop". (Nowadays the "master-slave" is omitted and we just call them flip-flops). Combined, the operation is such that as the first latch reads its input when the Latch Enable is low and the second latch follows the first latch when the Latch Enable is high, together they form an edge-sensitive memory element. To underline this edge sensitivity and to avoid any confusion, the "Latch Enable" signal was renamed to "Clock".

This edge-sensitive flip-flop is the basic founding memory element of all digital logic, and it's immensely useful. It's state is just about instantaneously set when there is a low-to-high transition in the Clock signal. And at all other times, it does not care what happens in its input. Now consider that you have a lot of flip-flops in a circuit, and a lot of control signals that "calculate" the input values to these groups of flip-flops which we can call "Registers".

It turns out that if there's just one signal named "Clock" which goes to all the Clock inputs of all the flip-flops in the system, the system, however large and complex may it be, is completely stable. Because the states of the registers can change only following the edge of the clock, there's "calculations", toggling, of the control signals only after the edge, and if sufficient time is allowed to pass between the edges, the signals settle to a fixed state before the next clock edge comes. With this system, you can design arbitrarily complex systems, limited only by the propagation delays and clock frequency. This style of one-clock design is called "synchronous" design and I would say it's the most important digital design methodology in use today.

Note: When this answer was written, there was no mention of Arduino in the question.

Where memory elements such as latches and flip-flops are involved, the terms clocking and latching describe what is the sensitivity of the memory element to the control signal, which is often labeled "Clock". In this context, "Clocking" means an edge-sensitive operation and "Latching" means a level-sensitive operation.

The most basic memory element is a form of positive feedback loop called a "Latch". One such element can be formed for example by cross-wiring two NAND gates so that the output of one holds the state of the other, and vice versa. It can be extended to become something called "D-Latch", which has a Data input and a Latch Enable input. Sometimes it's called a "D-follower", because for as long as the Latch Enable input is high, the output of the circuit "follows" the input of the circuit. But when the Latch Enable drops low, the output remains fixed - whatever was in the inputs when the Latch Enable drops from high to low, is "latched" into the element.

Now, consider that you would make another latch and invert its Latch Enable signal. You'd then have another latch which scans its inputs when the Latch Enable is low and holds its output when the Latch Enable is high. Understandable enough, right?

Finally, see what happens if you place this second latch "in front" of the first latch, so that he the output of the "active low" latch goes to the input of the "active high" latch. Connect the Latch Enable signals together. What you have formed is something that was originally called a "Master-Slave Latch" and quickly renamed to master-slave "Flip-Flop". (Nowadays the "master-slave" is omitted and we just call them "D flip-flops"). Combined, the operation is such that as the first latch reads its input when the Latch Enable is low and the second latch follows the first latch when the Latch Enable is high, together they form an edge-sensitive memory element. To underline this edge sensitivity and to avoid any confusion, the "Latch Enable" signal was renamed to "Clock".

This edge-sensitive flip-flop is the basic founding memory element of all digital logic, and it's immensely useful. It's state is just about instantaneously set when there is a low-to-high transition in the Clock signal. And at all other times, it does not care what happens in its input. Now consider that you have a lot of flip-flops in a circuit, and a lot of control signals that "calculate" the input values to these groups of flip-flops which we can call "Registers".

It turns out that if there's just one signal named "Clock" which goes to all the Clock inputs of all the flip-flops in the system, the system, however large and complex may it be, is completely stable. Because the states of the registers can change only following the edge of the clock, there's "calculations", toggling, of the control signals only after the edge, and if sufficient time is allowed to pass between the edges, the signals settle to a fixed state before the next clock edge comes. With this system, you can design arbitrarily complex systems, limited only by the propagation delays and clock frequency. This style of one-clock design is called "synchronous design" and I would say it's the most important digital design methodology in use today.

Where memory elements such as latches and flip-flops are involved, the terms clocking and latching describe what is the sensitivity of the memory element to the control signal, which is often labeled "Clock". In this context, "Clocking" means an edge-sensitive operation and "Latching" means a level-sensitive operation.

The most basic memory element is a form of positive feedback loop called a "Latch". One such element can be formed for example by cross-wiring two NAND gates so that the output of one holds the state of the other, and vice versa. It can be extended to become something called "D-Latch", which has a Data input and a Latch Enable input. Sometimes it's called a "D-follower", because for as long as the Latch Enable input is high, the output of the circuit "follows" the input of the circuit. But when the Latch Enable drops low, the output remains fixed - whatever was in the inputs when the Latch Enable drops from high to low, is "latched" into the element.

Now, consider that you would make another latch and invert its Latch Enable signal. You'd then have another latch which scans its inputs when the Latch Enable is low and holds its output when the Latch Enable is high. Understandable enough, right?

Finally, see what happens if you place this second latch "in front" of the first latch, so that he the output of the "active low" latch goes to the input of the "active high" latch. Connect the Latch Enable signals together. What you have formed is something that was originally called a "Master-Slave Latch" and quickly renamed to master-slave "Flip-Flop". (Nowadays the "master-slave" is omitted and we just call them flip-flops). Combined, the operation is such that as the first latch reads its input when the Latch Enable is low and the second latch follows the first latch when the Latch Enable is low, together they form an edge-sensitive memory element. To underline this edge sensitivity and to avoid any confusion, the "Latch Enable" signal was renamed to "Clock".

This edge-sensitive flip-flop is the basic founding memory element of all digital logic, and it's immensely useful. It's state is just about instantaneously set when there is a low-to-high transition in the Clock signal. And at all other times, it does not care what happens in its output. Now consider that you have a lot of flip-flops in a circuit, and a lot of control signals that "calculate" the input values to these groups of flip-flops which we can call "Registers".

It turns out that if there's just one signal named "Clock" which goes to all the Clock inputs of all the flip-flops in the system, the system, however large and complex may it be, is completely stable. Because the states of the registers can change only following the edge of the clock, there's "calculations", toggling, of the control signals only after the edge, and if sufficient time is allowed to pass between the edges, the signals settle to a fixed state before the next clock edge comes. With this system, you can design arbitrarily complex systems, limited only by the propagation delays and clock frequency. This style of one-clock design is called "synchronous" design and I would say it's the most important digital design methodology in use today.

Where memory elements such as latches and flip-flops are involved, the terms clocking and latching describe what is the sensitivity of the memory element to the control signal, which is often labeled "Clock". In this context, "Clocking" means an edge-sensitive operation and "Latching" means a level-sensitive operation.

The most basic memory element is a form of positive feedback loop called a "Latch". One such element can be formed for example by cross-wiring two NAND gates so that the output of one holds the state of the other, and vice versa. It can be extended to become something called "D-Latch", which has a Data input and a Latch Enable input. Sometimes it's called a "D-follower", because for as long as the Latch Enable input is high, the output of the circuit "follows" the input of the circuit. But when the Latch Enable drops low, the output remains fixed - whatever was in the inputs when the Latch Enable drops from high to low, is "latched" into the element.

Now, consider that you would make another latch and invert its Latch Enable signal. You'd then have another latch which scans its inputs when the Latch Enable is low and holds its output when the Latch Enable is high. Understandable enough, right?

Finally, see what happens if you place this second latch "in front" of the first latch, so that he the output of the "active low" latch goes to the input of the "active high" latch. Connect the Latch Enable signals together. What you have formed is something that was originally called a "Master-Slave Latch" and quickly renamed to master-slave "Flip-Flop". (Nowadays the "master-slave" is omitted and we just call them flip-flops). Combined, the operation is such that as the first latch reads its input when the Latch Enable is low and the second latch follows the first latch when the Latch Enable is high, together they form an edge-sensitive memory element. To underline this edge sensitivity and to avoid any confusion, the "Latch Enable" signal was renamed to "Clock".

This edge-sensitive flip-flop is the basic founding memory element of all digital logic, and it's immensely useful. It's state is just about instantaneously set when there is a low-to-high transition in the Clock signal. And at all other times, it does not care what happens in its input. Now consider that you have a lot of flip-flops in a circuit, and a lot of control signals that "calculate" the input values to these groups of flip-flops which we can call "Registers".

It turns out that if there's just one signal named "Clock" which goes to all the Clock inputs of all the flip-flops in the system, the system, however large and complex may it be, is completely stable. Because the states of the registers can change only following the edge of the clock, there's "calculations", toggling, of the control signals only after the edge, and if sufficient time is allowed to pass between the edges, the signals settle to a fixed state before the next clock edge comes. With this system, you can design arbitrarily complex systems, limited only by the propagation delays and clock frequency. This style of one-clock design is called "synchronous" design and I would say it's the most important digital design methodology in use today.

Where memory elements such as latches and flip-flops are involved, the terms clocking and latching describe what is the sensitivity of the memory element to the control signal, which is often labeled "Clock". In this context, "Clocking" means an edge-sensitive operation and "Latching" means a level-sensitive operation.

Where memory elements such as latches and flip-flops are involved, the terms clocking and latching describe what is the sensitivity of the memory element to the control signal, which is often labeled "Clock". In this context, "Clocking" means an edge-sensitive operation and "Latching" means a level-sensitive operation.

The most basic memory element is a form of positive feedback loop called a "Latch". One such element can be formed for example by cross-wiring two NAND gates so that the output of one holds the state of the other, and vice versa. It can be extended to become something called "D-Latch", which has a Data input and a Latch Enable input. Sometimes it's called a "D-follower", because for as long as the Latch Enable input is high, the output of the circuit "follows" the input of the circuit. But when the Latch Enable drops low, the output remains fixed - whatever was in the inputs when the Latch Enable drops from high to low, is "latched" into the element.

Now, consider that you would make another latch and invert its Latch Enable signal. You'd then have another latch which scans its inputs when the Latch Enable is low and holds its output when the Latch Enable is high. Understandable enough, right?

Finally, see what happens if you place this second latch "in front" of the first latch, so that he the output of the "active low" latch goes to the input of the "active high" latch. Connect the Latch Enable signals together. What you have formed is something that was originally called a "Master-Slave Latch" and quickly renamed to master-slave "Flip-Flop". (Nowadays the "master-slave" is omitted and we just call them flip-flops). Combined, the operation is such that as the first latch reads its input when the Latch Enable is low and the second latch follows the first latch when the Latch Enable is low, together they form an edge-sensitive memory element. To underline this edge sensitivity and to avoid any confusion, the "Latch Enable" signal was renamed to "Clock".

This edge-sensitive flip-flop is the basic founding memory element of all digital logic, and it's immensely useful. It's state is just about instantaneously set when there is a low-to-high transition in the Clock signal. And at all other times, it does not care what happens in its output. Now consider that you have a lot of flip-flops in a circuit, and a lot of control signals that "calculate" the input values to these groups of flip-flops which we can call "Registers".

It turns out that if there's just one signal named "Clock" which goes to all the Clock inputs of all the flip-flops in the system, the system, however large and complex may it be, is completely stable. Because the states of the registers can change only following the edge of the clock, there's "calculations", toggling, of the control signals only after the edge, and if sufficient time is allowed to pass between the edges, the signals settle to a fixed state before the next clock edge comes. With this system, you can design arbitrarily complex systems, limited only by the propagation delays and clock frequency. This style of one-clock design is called "synchronous" design and I would say it's the most important digital design methodology in use today.