Timeline for VHDL How to Design a Screen (Frame) Buffer
Current License: CC BY-SA 3.0
11 events
| when toggle format | what | by | license | comment | |
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| Dec 23, 2014 at 15:22 | vote | accept | Toygun Başaklar | ||
| Dec 23, 2014 at 15:22 | answer | added | Toygun Başaklar | timeline score: 0 | |
| Dec 21, 2014 at 6:12 | comment | added | mng | You should check everything where you are counting along the array, because something is getting misaligned. Try changing numbers and see how it affects the result. If you can't find anything wrong then you may have to look at the DVI interface too. | |
| Dec 19, 2014 at 21:23 | comment | added | Toygun Başaklar | @mng I couldn't solve the issue, and I am really upset now. Any advices on what to alter ? Thanks! | |
| Dec 18, 2014 at 1:45 | comment | added | mng | Sounds like you are off by a little bit in your vertical timing, most likely by 1. | |
| Dec 17, 2014 at 3:16 | history | edited | Toygun Başaklar | CC BY-SA 3.0 |
updated the question
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| Dec 16, 2014 at 21:46 | comment | added | Toygun Başaklar | @DaveTweed I edited my original question. Hope I added enough information! Thank you | |
| Dec 16, 2014 at 21:46 | history | edited | Toygun Başaklar | CC BY-SA 3.0 |
added 3378 characters in body
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| Dec 16, 2014 at 21:18 | comment | added | Dave Tweed | I take it you're only storing 1 bit per pixel, 16 pixels per storage location. If you're using "inferred" RAM, then yes, we need to see the code you're using. It would also help if you describe (or better yet, provide the code for) whatever's doing the writing, and why you believe the problem is writing and not reading. | |
| Dec 16, 2014 at 21:02 | review | First posts | |||
| Dec 16, 2014 at 21:06 | |||||
| Dec 16, 2014 at 20:57 | history | asked | Toygun Başaklar | CC BY-SA 3.0 |