Timeline for 150 MHz LVPECL Clock
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jan 16, 2015 at 9:26 | comment | added | Andy aka | It's the receiving device that needs to be analysed. The clock data sheet says LVPECL and it may be compatible but it might need capacitively coupling and termination resistors adding. It can be tricky to analyse. | |
| Jan 16, 2015 at 8:59 | comment | added | Oshi | Can this oscillator be used for above specification ::- txccrystal.com/images/pdf/bb.pdf | |
| Jan 16, 2015 at 8:34 | comment | added | Andy aka | Without spilling the beans on the device nobody can say. | |
| Jan 16, 2015 at 4:21 | comment | added | Oshi | Does this common mode voltage i.e. average DC level is the supply voltage Vcc I have to look @ in the datasheet? | |
| Jan 15, 2015 at 16:50 | comment | added | Michael Karas | The common mode range of the input generally has to include the amplitude of the differential signal. So you would not be able to apply a clock with average DC level of 3.0 volts with an amplitude over zero volts. If the average DC level was 2.5V then the input amplitude could not exceed 0.5V above the DC level. | |
| Jan 15, 2015 at 13:51 | history | answered | Andy aka | CC BY-SA 3.0 |