Timeline for How to find gate delay for 4-bit look-ahead carry adder?
Current License: CC BY-SA 3.0
11 events
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| Feb 24, 2015 at 19:08 | history | edited | tcrosley | CC BY-SA 3.0 |
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| Feb 24, 2015 at 19:08 | comment | added | tcrosley | @RohitGulabwani yes, I agree, you want to use the maximum for any bit, which is 6. | |
| Feb 24, 2015 at 18:43 | comment | added | Rohit Gulabwani | I am confused sir my question is to find gate delays occur in computing bit1 of the sum by a 4-bit look-ahead carry adder? (bit0 is the LSB) so for that i guess i am getting 6. Am i correct? | |
| Feb 24, 2015 at 18:36 | comment | added | tcrosley | If you are referring to input bit 1 (A2/B2 in the diagram), then answer is 6, from A2/B2 to S3. If you are talking about output bit 1 (S2 in the diagram), then you are also talking maximum of 6 (A1/B1 to S2). If you are talking both input bit 1 (A2/B2) to output bit 1 (S2), the answer is 5. | |
| Feb 24, 2015 at 18:30 | comment | added | Rohit Gulabwani | So what is the one i need to consider if i am asked the question gate delays occur in computing bit1 of the sum by a 4-bit look-ahead carry adder?LSB being 0. | |
| Feb 24, 2015 at 18:28 | comment | added | tcrosley | The maximum path from A2 or B2 to S2 is 5 (I was using S3 before, which was 6). The maximum from A1 or B1 to S2 is 6. | |
| Feb 24, 2015 at 18:27 | comment | added | Rohit Gulabwani | Thank You sir i think i got it. So the final answer for S2 will be 6. | |
| Feb 24, 2015 at 18:23 | comment | added | Rohit Gulabwani | sir i need to find for S2 from your diagram as LSB in my case is zero. | |
| Feb 24, 2015 at 18:15 | vote | accept | Rohit Gulabwani | ||
| Feb 24, 2015 at 18:57 | |||||
| Feb 24, 2015 at 18:08 | vote | accept | Rohit Gulabwani | ||
| Feb 24, 2015 at 18:14 | |||||
| Feb 24, 2015 at 18:04 | history | answered | tcrosley | CC BY-SA 3.0 |