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Apr 4, 2015 at 12:38 comment added Sidd I'm still confused, in the image in my question, after the first NMOS the voltage is VDD-Vth, after the second NMOS shouldn't the voltage be VDD-2Vth?
Apr 4, 2015 at 12:33 history edited carveone CC BY-SA 3.0
added 160 characters in body
Apr 4, 2015 at 12:30 comment added carveone @RogerC. Thanks. The three FETs in the row confused me a little. I've an urge to edit my answer (which was way too hasty) but to reflect these comments. I'll just refer to them. Sidd - yes, that's right.
Apr 4, 2015 at 12:29 comment added Roger C. @Sidd, yes it is 6.3 V, assuming ideal NMOS transistors where RDSON=0 ohms.
Apr 4, 2015 at 12:25 comment added Roger C. @carveone, that's it. It will then come to an equilibrium with VGS=Vth.
Apr 4, 2015 at 12:23 comment added Sidd @carveone So the first part of the question, the voltage will be 6.3 right?
Apr 4, 2015 at 12:22 comment added carveone @RogerC. Ah I see. My initial impulse was that if the load was passive, the voltage at the right would rise to Vdd. Which would switch the FETs off which would, um, cause the voltage to fall to 0 which would... Er. Ok, I'm evidently having a senior-moment-morning :-)
Apr 4, 2015 at 12:19 history edited carveone CC BY-SA 3.0
Too many edits !
Apr 4, 2015 at 12:18 comment added Roger C. Actually, I'm not assuming that the voltage at the right is being held by an external reference. On the contrary, I assume that the load is passive. The voltage at the right comes from the left, but it cannot be above VDD-Vth.
Apr 4, 2015 at 12:13 comment added carveone @nidhin: Doh! I need more sleep. Editing post.
Apr 4, 2015 at 12:13 history edited carveone CC BY-SA 3.0
added 289 characters in body
Apr 4, 2015 at 12:11 comment added nidhin Field Effect Transistor is not a transistor?!!!
Apr 4, 2015 at 12:10 history answered carveone CC BY-SA 3.0