Timeline for VHDL - Why does frequency divider counter max at one less than half period?
Current License: CC BY-SA 3.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 20, 2015 at 4:44 | vote | accept | Kvass | ||
| Apr 20, 2015 at 2:41 | answer | added | alex.forencich | timeline score: 1 | |
| Apr 20, 2015 at 2:03 | comment | added | The Photon | It sounds like your source is confused. At one point they say they count from 1 to 124999, but then later they imply they actually count from 0 to 124999. | |
| Apr 20, 2015 at 1:56 | history | asked | Kvass | CC BY-SA 3.0 |