Timeline for Verilog Assignment
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| May 15, 2015 at 8:24 | history | edited | apalopohapa | CC BY-SA 3.0 |
added 1 character in body
|
| May 15, 2015 at 8:09 | comment | added | apalopohapa |
@user1222049 Yes. 0: begin state <= 1; C_output <= 0; R <= ({F_input, 2'b00} + F_input) - 160; end 1: if (R > 9) begin R <= R - 9; C_output <= C_output + 1; end
|
|
| May 15, 2015 at 8:03 | comment | added | Sagistic | Is it possible to reduce it to just 2 states? | |
| May 15, 2015 at 8:01 | history | edited | apalopohapa | CC BY-SA 3.0 |
edited body
|
| May 15, 2015 at 8:01 | vote | accept | Sagistic | ||
| May 15, 2015 at 7:38 | history | answered | apalopohapa | CC BY-SA 3.0 |