I had this problem recently and still couldn't find an answer in 2015, so I have updated this thread.

I actually read the register with a scope so not sure exactly when the data is clocked out, but I do know this device and suggest it will do one of the following.

CS Low, then clock 0x0000 into the MRF. While you do this capture the SDO from the MRF. Some registers clock out a byte during the second half of the write, ie on clocks 8-15 of the command word (the Rx FIFO register for example), but as the status word is 16 bits you may have to clock it out after the command. You do have to clock it out. Interrupt status will be a 16 bit word somewhere in the 32 clocks.

I had this problem recently and still couldn't find an answer in 2015, so I have updated this thread.

I actually read the register with a scope so not sure exactly when the data is clocked out, but I do know this device and suggest it will do one of the following.

CS Low, then clock 0x0000 into the MRF. While you do this capture the SDO from the MRF. Some registers clock out a byte during the second half of the write, ie on clocks 8-15 of the command word (the Rx FIFO register for example), but as the status word is 16 bits you may have to clock it out after the command.

Just checked, the Status word clocks out as you clock in 0x0000 with MSB actually present on SDO when CS=0. (all other command words start with a 1, by default status word is presented)