Timeline for Highest ADC input signal frequency for atmega8?
Current License: CC BY-SA 3.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Apr 13, 2017 at 12:32 | history | edited | CommunityBot |
replaced http://electronics.stackexchange.com/ with https://electronics.stackexchange.com/
|
|
| Aug 5, 2011 at 3:31 | comment | added | Kevin Vermeer | @tyblu - That should really be an answer, especially if you improved it by providing a reference for your claim that the maximum ADC clock is 1MHz. | |
| Aug 5, 2011 at 2:57 | comment | added | tyblu | It takes 14 clock cycles to take a measurement with its particular ADC module in free-running mode (Fig. 101 in datasheet). The max. ADC clock is 1MHz (3LSB or 3/2^8=1.2% error), giving 71428 SPS, and 35714 Hz. | |
| Aug 4, 2011 at 20:31 | history | answered | Kellenjb | CC BY-SA 3.0 |