Oh, be careful with the NXP SPI controllers. I can only tell from experience with the LPC1768 but it seems that at least one of the two SPI peripherals are identical.
As said, there are two SPI controllers in your chip. I can't tell much about the first one (the ordinary SPI controller without FIFO). It may just work for your task, but - no FIFO, so very high CPU load.
The second one, called SPI1/SSP, is tricky because it demands that the chip-select line goes high between each transfer word for at least one clock cycle. This makes it impossible to transfer a continuous bit-stream without gaps. You will not be able to directly interface I2S in SPI mode.
You can however configure the SPI1/SSP in TI SSI mode. In this mode the chip-select line becomes a frame syncronization signal that stays low most of the time but pulses high on each least significant bit. The transfer will be continuous without single bit gaps so it interfaces nicely with your I2C codec.
You may be able to derive the I2S Word-Select signal from this using a single divider flip-flop. Deriving directly from clock like you suggested would work just as well.
I suggest that you take a look at figure 26 in the user manual UM10120:
