Timeline for Changing flash latency from 0 to 1 even with enabled prefetch slows execution on STM32
Current License: CC BY-SA 3.0
11 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| S Jul 25, 2015 at 17:43 | history | bounty ended | hak8or | ||
| S Jul 25, 2015 at 17:43 | history | notice removed | hak8or | ||
| Jul 25, 2015 at 17:43 | vote | accept | hak8or | ||
| Jul 24, 2015 at 18:34 | answer | added | asndre | timeline score: 2 | |
| Jul 22, 2015 at 23:32 | comment | added | hak8or | I thought I saved the data related to when I change the wait state to 2 nut it seems I didn't. From what I remember, it was 1.2 to 1.5 seconds. I will recheck when I get home. | |
| Jul 21, 2015 at 22:01 | comment | added | rdtsc | The datasheet is not very helpful. My guess would be that the flash bus clock is delayed by 1 Tcy for FLASH_ACR = 0x01, and delayed by 2 for 0x02, regardless of prefetch. Did you try 0x02 to see if it degrades another 66%? | |
| Jul 21, 2015 at 14:01 | history | tweeted | twitter.com/#!/StackElectronix/status/623493124409688065 | ||
| S Jul 21, 2015 at 3:03 | history | bounty started | hak8or | ||
| S Jul 21, 2015 at 3:03 | history | notice added | hak8or | Draw attention | |
| Jul 19, 2015 at 2:16 | history | edited | hak8or | CC BY-SA 3.0 |
Added more detail
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| Jul 19, 2015 at 2:10 | history | asked | hak8or | CC BY-SA 3.0 |