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Feb 1, 2018 at 0:31 history edited Damien CC BY-SA 3.0
Fix typo
Apr 13, 2017 at 12:32 history edited CommunityBot
replaced http://electronics.stackexchange.com/ with https://electronics.stackexchange.com/
Aug 22, 2015 at 2:43 comment added Paebbels Hello again. I updated the PoC sources and my answer to address the Altera specific synchronizers. Currently these circuits work in a StratixIV design on a DE4 board.
Aug 17, 2015 at 5:27 vote accept Damien
Aug 17, 2015 at 4:12 history edited Damien CC BY-SA 3.0
Typo fix.
Aug 14, 2015 at 0:54 comment added Paebbels I updated the synchronizer modules in our PoC-Library and uploaded the first changes to GitHub. Thanks for the link to Altera's attributes.. I'll test it in a Stratix IV design and update my post if everything works as espected. Currently, my design crashes Quartus so it's hard to find the faulty code line (Xilinx compiles my VHDL files without complains).
Aug 13, 2015 at 6:48 comment added Damien See this question where an answer lists several altera attributes for synchronisation.
Aug 11, 2015 at 16:38 answer added Paebbels timeline score: 9
Aug 11, 2015 at 12:21 history tweeted twitter.com/#!/StackElectronix/status/631077958812368896
Aug 11, 2015 at 6:41 history edited Damien CC BY-SA 3.0
Clarify title.
Aug 11, 2015 at 6:41 comment added Damien A std_logic_vetor. I have naievely implented the four-phase handshaking synchroniser from this paper which simulates correctly, but I'm not convinced that I have "told" the FPGA everything it needs to know to synthsize correctly.
Aug 11, 2015 at 6:25 comment added Paebbels What kind of signal do you want to synchronize? A strobe, a flag, a counter value, a bit vector or something more complex?
Aug 11, 2015 at 3:53 history edited Damien CC BY-SA 3.0
Add extra link, clarify the question is for an Altera device.
Aug 11, 2015 at 3:47 history asked Damien CC BY-SA 3.0