The gate does not generate power. This is how a NOT gate might look inside (from Wikipedia):
When A = 0 (an off input), the transistor on the top conducts and the bottom transistor doesn't, thus Q will be approximatelly Vdd (used Falstad's circuit simulator to get this image and the next one).
The opposite is true, when A = 1, the transistor on the bottom conducts and the transistor on the top doesn't, giving Q = Vss.
The gate does not generate power. This is how a NOT gate might look inside (from Wikipedia):
When A = 0 (an off input), the transistor on the top conducts and the bottom transistor doesn't, thus Q will be approximatelly Vdd.
The opposite is true, when A = 1, the transistor on the bottom conducts and the transistor on the top doesn't, giving Q = Vss.
The gate does not generate power. This is how a NOT gate might look inside (from Wikipedia):
When A = 0 (an off input), the transistor on the top conducts and the bottom transistor doesn't, thus Q will be approximatelly Vdd (used Falstad's circuit simulator to get this image and the next one).
The opposite is true, when A = 1, the transistor on the bottom conducts and the transistor on the top doesn't, giving Q = Vss.
The gate does not generate power. This is how a NOT gate might look inside (from Wikipedia):
When A = 0 (an off input), the transistor on the top conducts and the bottom transistor doesn't, thus Q will be approximatelly Vdd.
The opposite is true, when A = 1, the transistor on the bottom conducts and the transistor on the top doesn't, giving Q = Vss.
