Timeline for How a 2-1 multiplexer (MUX) work?
Current License: CC BY-SA 3.0
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| Aug 30, 2011 at 14:33 | comment | added | supercat | @stevenvh: Logic compilers generally have options to indicate whether such terms must be kept (or even to indicate that they should be added when they don't exist). If the output of the circuit is going to be 'don't-care' any time S changes, the gate may be omitted. In the one circuit I designed with a mux as a latch, I used a small RC delay to cover the hazard condition. Actually, it was a cute memory-controller circuit. One chip generated two outputs: one of which was simply the inverse of A12, and the other of which was a latch which was strobed only when A12 was low and A11 high. | |
| Aug 30, 2011 at 14:25 | comment | added | stevenvh | Standard HCMOS devices like the 74HC157 don't seem to have this third AND term, or at least it isn't shown in the logic diagram. I also wonder if an FPGA synth won't optimize it away. | |
| Aug 30, 2011 at 12:49 | history | answered | supercat | CC BY-SA 3.0 |