This sounds as if the conversion clock is used for each bit of the conversion.

It appears that 12 clock cycles are required for an 8 bit conversion and 14 clock cycles for a 10 bit conversion.

This means that the conversion needs 1 clock per conversion bit plus an overhead (for sample time and register setup perhaps) of 4 clock cycles.

If you identify thr ADC I could be more specific.

This sounds as if the conversion clock is used for each bit of the conversion.

It appears that 12 clock cycles are required for an 8 bit conversion and 14 clock cycles for a 10 bit conversion.

This means that the conversion needs 1 clock per conversion bit plus an overhead (for sample time and register setup perhaps) of 4 clock cycles.

If you identify the ADC I could be more specific.

Update: Useful link

There is an excellent application note from Freescale on this module, which is used in a number of their microcontrollers. You will find the relevant formula for this successive approximation device on page 11. The minimum time for a conversion is attained when the minimum possible number of sample clocks is specified.

Table 2 has more details of how the timings are broken down.

HTH