Timeline for Error in this Countdown module? (Verilog)
Current License: CC BY-SA 3.0
9 events
| when toggle format | what | by | license | comment | |
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| Nov 7, 2015 at 18:38 | comment | added | johnnymopo | Added code suggestion | |
| Nov 7, 2015 at 18:32 | history | edited | johnnymopo | CC BY-SA 3.0 |
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| Nov 7, 2015 at 18:21 | history | edited | johnnymopo | CC BY-SA 3.0 |
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| Nov 7, 2015 at 17:48 | history | edited | johnnymopo | CC BY-SA 3.0 |
added code block from text suggestion
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| Nov 7, 2015 at 15:43 | comment | added | The Photon |
@johnnymopo, I think your answer would be more clear if you included the always @(<xxx>) that you recommend.
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| Nov 7, 2015 at 15:16 | comment | added | johnnymopo | @dave tweed, how would you write this to avoid a latch at all if you want to make synchronous logic with a common clock domain? cd has to be something.... I ask as I do this and it seems to work well, at least to 125 MHz where I've been working at. But I have no formal vhdl training. | |
| Nov 7, 2015 at 12:01 | comment | added | Dave Tweed |
Just to be clear, adding else cd <= cd; still creates a latch; all you've done is make it explicit rather than implicit. In general, combinatorial latches created in this way should be avoided.
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| Nov 7, 2015 at 7:05 | comment | added | Meridian | johnnymopo, thank you for your reply. The revised code still brought about an inferred latch (see ThePhoton above). And CLOCK_50 (50 MHz) would have been too fast for the countdown. But thanks to your suggestion of using posedge, I managed to figure it out. So wherever you are in this world, I wish the best of luck to you and thanks again for helping out a random stranger. | |
| Nov 7, 2015 at 5:40 | history | answered | johnnymopo | CC BY-SA 3.0 |