Timeline for FPGA + SRAM - floating inputs of SRAM during configuration of FPGA
Current License: CC BY-SA 3.0
12 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Nov 24, 2015 at 17:04 | comment | added | alex.forencich | Yep. I think that would end up being an address timed read and a we timed write. Should work just fine. | |
| Nov 24, 2015 at 11:51 | comment | added | zupazt3 | Ok, I will tie them to ground then. So - if I want to use only write cycle 1 - I can also tie #CE to ground? Am I correct? (I have limited pins on FPGA and it would be desired for me to not use more pins then I have to). | |
| Nov 24, 2015 at 1:33 | comment | added | alex.forencich | Ah, that's on page 9. I think it's just strangely worded. I think it should be more like "WE or CE or (LB and UB) must be high during all address transitions" as this actually matches the timing diagrams. It's a very standard requirement - the write condition cannot be commanded during an address change. A just checked a cypress datasheet for a different async sram, "R/W or CE must be HIGH during all address transitions". | |
| Nov 24, 2015 at 1:15 | comment | added | zupazt3 | Super! Thx again. And it's written on page 7, "Notes : 1.WE#,CE#, LB#, UB# must be high during all address transitions." And it is labeled as "point 1" (1.) and this point 1 is listed in all three methods of write cycles - that's why I thought it was respective for all writes. But it doesn't seem very logical so I guess you're right. And - have to admit - I didn't know that this waveform with one diagonal line means "don't care"... | |
| Nov 23, 2015 at 23:42 | comment | added | alex.forencich | Looks like the only cycle where it 'has' to be set to 1 is for write cycle 3, where the write is controlled by the LB and UB signals. However, you don't need to use that mode. Any other read or write cycle has LB and UB as 'don't care' outside of the actual operation. So just use the WE or CE gated read/write, and you will be fine to tie those to GND. | |
| Nov 23, 2015 at 23:33 | comment | added | alex.forencich | Where does it say that in the datasheet? | |
| Nov 23, 2015 at 23:27 | vote | accept | zupazt3 | ||
| Nov 23, 2015 at 23:27 | comment | added | zupazt3 | Thanks for answers. Data stored in SRAM can be corrupted or even completely erased during configuration - they don't even have any sense at this time (FPGA will fill them after start-up). My only concern was to not damage permanently the RAM or something like this. By the way, side question, can I tie DQM (/LB & UB) lines to GND so that outputs are enabled all the time? I only use 16-bit data, but datasheet for my LY61L102416A says that it should be high during address transitions - but I'm not sure whether it is neccesary or can I just drive them low all the time. | |
| Nov 23, 2015 at 22:57 | comment | added | alex.forencich | Well, leaving them floating for a short period of time is probably OK. However, if you tie HSWAPEN to ground, the FPGA pins will be pulled high before and during configuration, so the pins should never be floating unless the FPGA design leaves them floating. In which case I would think the worst that would happen is increased power draw from the SRAM and possibly corrupted memory contents. | |
| Nov 23, 2015 at 19:35 | comment | added | zupazt3 | And what if FPGA is turned off? If I set CE (chip enable) of SRAM to high, then address lines can be floating? | |
| Nov 23, 2015 at 19:29 | history | edited | alex.forencich | CC BY-SA 3.0 |
added 75 characters in body
|
| Nov 23, 2015 at 19:21 | history | answered | alex.forencich | CC BY-SA 3.0 |