Timeline for Verilog and break statements is there a possible alternative?

7 events

when toggle format	what		by	license	comment
Mar 17 at 1:45	comment	added	None		"Break statements don't make sense in HDL", you're the one who sounds beginner. `break` makes a lot of sense and is widely used. Using `casex casez` without `unique`, it's even necessary if you don't want to have several cases selected.
May 24, 2020 at 17:06	comment	added	EML		Verilog is a procedural language; the LRM says, verbatim, that "Verilog behavioural models contain procedural statements". It was written as a simulation language. The lack of a `break` is essentially an oversight, which was fixed in SV. You can get the same behaviour with `disable`. The OPs problem is that he's trying to write synthesisable code, and he doesn't understand what can and what can't be synthesised.
Dec 21, 2015 at 0:32	vote	accept	ExchangeChri
Dec 21, 2015 at 0:32	vote	accept	ExchangeChri
Dec 21, 2015 at 0:32
Dec 16, 2015 at 21:22	comment	added	Spoon		Think.. all code executes every clock cycle... and I mean every cycle. Indeed even faster than every cycle... no sequential execution unless you design it in. There are caveats.
Dec 16, 2015 at 17:18	history	edited	Tom Carpenter	CC BY-SA 3.0	added 1258 characters in body
Dec 16, 2015 at 17:10	history	answered	Tom Carpenter	CC BY-SA 3.0