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Andy aka
Andy aka
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You can make a voltage controlled oscillator (VCO) to run at any frequency thatwhere there is readily available technology. You input a voltage and out comes a certain frequency. If you increase the voltage, the output frequency rises. You drop the control voltage and the frequency drops. In the case of this question we're talking about frequencies way-above normal clock speeds of MCUs.

If you then "sniff" and divide down that output frequency down to a much lower frequency of (say) 10MHz using digital clock dividers then you can use simple logic gates to compare that divided down frequency with a rock-solid 10MHz xtal-based clock. There are various digital ways of doing this but the bottom line is, after filtering/processingprocessing that "comparison" signal, you can use a version of it to nudge (or align) the VCO with an exact and desired multiple of your reference 10MHz clock.

In this way, you get a very stable, very high frequency that the MCU (or FPGA or logic chip) doesn't really know anything about but has assisted along the way to produce. It's called a phase locked loop or PLL.

You can make a voltage controlled oscillator (VCO) to run at any frequency that there is readily available technology. You input a voltage and out comes a certain frequency. If you increase the voltage the output frequency rises. You drop the control voltage and the frequency drops.

If you then divide down that output frequency to a much lower frequency of (say) 10MHz using digital clock dividers then you can use simple logic gates to compare that divided down frequency with a rock-solid 10MHz xtal-based clock. There are various digital ways of doing this but the bottom line is, after filtering/processing that "comparison" signal, you can use a version of it to nudge (or align) the VCO with an exact desired multiple of your reference 10MHz clock.

In this way, you get a very stable, very high frequency that the MCU (or FPGA or logic chip) doesn't really know anything about but has assisted along the way to produce. It's called a phase locked loop or PLL.

You can make a voltage controlled oscillator (VCO) to run at any frequency where there is readily available technology. You input a voltage and out comes a certain frequency. If you increase the voltage, the output frequency rises. You drop the control voltage and the frequency drops. In the case of this question we're talking about frequencies way-above normal clock speeds of MCUs.

If you then "sniff" and divide that output frequency down to a much lower frequency of (say) 10MHz using digital clock dividers then you can use simple logic gates to compare that divided down frequency with a rock-solid 10MHz xtal-based clock. There are various digital ways of doing this but the bottom line is, after processing that "comparison" signal, you can use a version of it to nudge (or align) the VCO with an exact and desired multiple of your reference 10MHz clock.

In this way, you get a very stable, very high frequency that the MCU (or FPGA or logic chip) doesn't really know anything about but has assisted along the way to produce. It's called a phase locked loop or PLL.

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Andy aka
Andy aka
  • 473.1k
  • 29
  • 383
  • 839

You can make a voltage controlled oscillator (VCO) to run at any frequency that there is readily available technology. You input a voltage and out comes a certain frequency. If you increase the voltage the output frequency rises. You drop the control voltage and the frequency drops.

If you then divide down that output frequency to a much lower frequency of (say) 10MHz using digital clock dividers then you can use simple logic gates to compare that divided down frequency with a rock-solid 10MHz xtal-based clock. There are various digital ways of doing this but the bottom line is, after filtering/processing that "comparison" signal, you can use a version of it to nudge (or align) the VCO with an exact desired multiple of your reference 10MHz clock.

In this way, you get a very stable, very high frequency that the MCU (or FPGA or logic chip) doesn't really know anything about but has assisted along the way to produce. It's called a phase locked loop or PLL.