Timeline for Preventing Altium via stitching on the designators
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
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| Jun 11, 2020 at 15:10 | history | edited | CommunityBot |
Commonmark migration
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| Dec 24, 2015 at 20:19 | comment | added | The Photon | To be honest, I've only used Altium stitching via generation once and I wasn't impressed. I think the real solution is to add stitching vias manually. It's pretty quick to just shelve polygons, turn on all the layers you're worried about not colliding with, and punch down a bunch of vias wherever you want them. | |
| Dec 24, 2015 at 19:54 | comment | added | Armandas | @Asmyldof How is an Electrical Clearance rule going to work with a silkscreen object? | |
| Dec 24, 2015 at 18:02 | comment | added | Asmyldof | @ThePhoton But then it'll only highlight, right? The OP wanted to have no stiches because else move text. I mean, I've been dragging refdes and print around the majority of my life and happy to do it for proper design, but still... Question, answer. | |
| Dec 24, 2015 at 17:22 | comment | added | The Photon | I dont' think you'd use a clearance rule. You'd use the silkscreen over soldermask opening rule. | |
| Dec 24, 2015 at 15:30 | comment | added | Asmyldof | @Armandas they are there. I don't know what you lot call your layers, so I cannot fill that in for you. Nor do I know what you put on the silkscreen with which properties. | |
| Dec 24, 2015 at 13:22 | comment | added | Armandas | You'll get my up vote if you can post the exact queries to use with the clearance rule. | |
| Dec 24, 2015 at 12:10 | history | answered | Asmyldof | CC BY-SA 3.0 |