Timeline for UART Receiver Sampling Rate

6 events

when toggle format	what		by	license	comment
Dec 25, 2015 at 23:51	vote	accept	chasep255
Dec 25, 2015 at 15:58	comment	added	WhatRoughBeast		Let's say your UART is working at 9600 baud. Then one data cell is 104 usec. A 100 MHz clock will require 104,000 clock cycles to deal with the UART data, and this in turn needs a 17-bit counter. You may find this a bit wasteful of resources, and performing the necessary logic at 100 MHz may be a pain, but it's your choice. This sort of tradeoff (extra FPGA resources vs external slow clock) is exactly what design engineers do for a living. And, of course, there's nothing preventing you from dividing down your 100 MHz internally to make the UART logic more compact.
Dec 25, 2015 at 15:23	history	edited	Andy aka	CC BY-SA 3.0	added 543 characters in body
Dec 25, 2015 at 14:54	comment	added	Andy aka		I understand but you have to weigh up hardware stuff like - is it more efficient to divide down to a lower frequency and use smaller counts with less hardware and less current consumption.
Dec 25, 2015 at 14:52	comment	added	chasep255		I just figured it is easier to just sample at the 100 Mhz clock I already have rather than create a module to divide it up.
Dec 25, 2015 at 14:50	history	answered	Andy aka	CC BY-SA 3.0