Wow, I had to check my calendar to be sure it wasn't 1976.

The 74LS family is well past it's best-before date. It's a DTL family (pretending to be TTL). As such an 'open' input is interpreted as a logic 1. If you leave both inputs open, and are using a 74LS00, it will do what NAND gates do with two '1' inputs and drive the output low. Ground either of the two inputs to a NAND gate and the output should go high.

In general you will be a lot less frustrated if you always connect every in put to a logic 1 or logic 0, including unused inputs. That will come in especially handy with CMOS (eg. 74HC00) where the inputs can do odd things if you let them float.

Schematic of 74LS00 gate (from the datasheet):

Wow, I had to check my calendar to be sure it wasn't 1976.

The 74LS family is well past its best-before date. It's a DTL family (pretending to be TTL). As such an 'open' input is interpreted as a logic 1. If you leave both inputs open, and are using a 74LS00, it will do what NAND gates do with two '1' inputs and drive the output low. Ground either of the two inputs to a NAND gate and the output should go high.

In general you will be a lot less frustrated if you always connect every in put to a logic 1 or logic 0, including unused inputs. That will come in especially handy with CMOS (eg. 74HC00) where the inputs can do odd things if you let them float. For TTL families and LSxx, ground or tie inputs high through 1K. For CMOS tie high or low directly or through a resistor.

Schematic of 74LS00 gate (from the datasheet):