Timeline for Does a CPU completely freeze when using a DMA?
Current License: CC BY-SA 3.0
15 events
when toggle format | what | by | license | comment | |
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S Jan 20, 2016 at 12:19 | history | suggested | Photon001 |
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Jan 20, 2016 at 11:26 | history | tweeted | twitter.com/StackElectronix/status/689770862321475584 | ||
Jan 20, 2016 at 9:42 | comment | added | pipe | @DaveTweed Nope. If you look at the bus timings for the 68000, each "bus cycle" (read or write) is divided into 8 states, taking a minimum of 4 actual clock cycles, of which only some of them drives the data bus. This multiplexing does require some extra hardware though, because it drives the address bus all the time. | |
Jan 20, 2016 at 9:18 | review | Suggested edits | |||
S Jan 20, 2016 at 12:19 | |||||
Jan 20, 2016 at 8:16 | comment | added | MSalters | Modern CPU's have caches that on average resolve 95% of memory accesses. As long as the CPU doesn't need RAM, DMA isn't interfering anyway. | |
Jan 20, 2016 at 4:57 | answer | added | old_timer | timeline score: 0 | |
Jan 20, 2016 at 3:29 | comment | added | Dave Tweed | @pipe: That doesn't sound right. The Amiga used an M68K CPU, which has a completely asynchronous bus. You might be thinking of the Apple II, which took advantage of the fact that its 6502 CPU only uses the bus for half of each clock cycle, and used the other half for the video output, which also served to keep the DRAM refreshed. | |
Jan 20, 2016 at 0:14 | vote | accept | Mahkoe | ||
Jan 19, 2016 at 21:01 | answer | added | micheal65536 | timeline score: 19 | |
Jan 19, 2016 at 20:07 | answer | added | user39382 | timeline score: 2 | |
Jan 19, 2016 at 17:41 | comment | added | pipe | The Amiga home computer got around this by observing that the CPU used actually only accessed the bus two cycles, then stayed off the bus for two cycles, when still running at the full speed. The DMA-based peripherals (graphics, audio, disk) used the cycles in between. Not an answer to your question since the question is hypothetical and computers are always ruined by practical details. :) | |
Jan 19, 2016 at 17:17 | answer | added | user15426 | timeline score: 21 | |
Jan 19, 2016 at 16:40 | answer | added | NeinDochOah | timeline score: 3 | |
Jan 19, 2016 at 16:39 | comment | added | Dave Tweed | Yes. The DMA rarely runs at the full bandwidth of the memory. It just steals a cycle (or a burst of cycles) every now and then, controlled by the rate of the I/O device. | |
Jan 19, 2016 at 16:25 | history | asked | Mahkoe | CC BY-SA 3.0 |