Timeline for What would make me choose Verilog or VHDL over schematic design on CPLDs or FPGAs?
Current License: CC BY-SA 3.0
3 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 22, 2016 at 20:10 | review | Low quality posts | |||
| Feb 23, 2016 at 5:08 | |||||
| Feb 22, 2016 at 19:55 | review | First posts | |||
| Feb 22, 2016 at 20:08 | |||||
| Feb 22, 2016 at 19:51 | history | answered | valplo | CC BY-SA 3.0 |