Timeline for Why do CPU's typically connect to only one bus?
Current License: CC BY-SA 3.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Feb 26, 2016 at 8:10 | comment | added | Peter Smith | Even though slow buses do not require fast silicon, it is not uncommon to find very fast drivers on slow interfaces, which can create a major headache for PCB layout. I have seen ordinary PCI (max speed 133MHz on PCI-X) with rise and fall times of less than 300 ps, as the vendors are using a standard I/O cell. I know PCI, as an interface, is not normally available on new processors, but this issue is applicable elsewhere. | |
| Feb 26, 2016 at 3:30 | comment | added | uint128_t | A fast bus would typically be part of a high-performance device e.g. a CPU. The bus interface requires space and connections to other parts of the chip. Silicon area on a processor die is much more expensive than a much slower chip, because the process size is smaller and fabrication/packaging is more difficult. Therefore, it's cheaper to restrict the devices on the FSB to only those devices that actually require such bandwidth. However, as more controllers are integrated with the CPU on the same die (a SoC), this is no longer as true. | |
| Feb 26, 2016 at 3:25 | comment | added | DrZ214 |
Fast buses require fast silicon, slow buses don't What exactly does fast silicon mean? Higher-purity silicon? Or are you saying slow buses can use a different element than silicon? Either way, I thought silicon was a pretty cheap material. Interesting bit about the watchdog too. I might ask a related question about it.
|
|
| Feb 26, 2016 at 3:02 | history | edited | uint128_t | CC BY-SA 3.0 |
Expanded a wee bit
|
| Feb 26, 2016 at 2:56 | history | answered | uint128_t | CC BY-SA 3.0 |