Timeline for Why do CPU's typically connect to only one bus?
Current License: CC BY-SA 3.0
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| Feb 6, 2018 at 6:20 | comment | added | user39382 | "Are there any CPU packages available today with perhaps 800 pins?" Oh yes. Packages with 1100+ pins were already commonplace when this answer was written. And nowadays, there's LGA3647 for some Skylake-EX server CPUs… | |
| Apr 5, 2017 at 18:18 | comment | added | Oskar Skog | Why wouldn't there be? A 32x32 ball grid array and multi layered PCB doesn't sound like a difficult problem (on a relative scale). The hardware engineers are amazing. // Think about how wide and clumsy RAM cards can be, and still clock in at 1.6 GHz (625 picoseconds). If the electric signals travel at 2/3 c, the longest trace can only be 6 cm long, and just a few mm difference in length will cause noticeable timing offsets. // And I'd guess that the crosstalk between layers wouldn't be much worse than between traces on the same layer. | |
| Mar 3, 2016 at 21:46 | history | answered | user6030 | CC BY-SA 3.0 |