It's closest to an SR latch, but instead of being made with NAND/NOR it's made with two inverters.
The transistors M5 and M6 have higher drive than the output of inverters (M1/M2 and M3/M4) overriding the output 1 or 0 and setting a new one, which is then reinforced by the M1/M2 M3/M4 "latch".
See the answers herehere and herehere also.