Timeline for How do I drive 14.3Mhz clock input from 10MHz?
Current License: CC BY-SA 3.0
8 events
| when toggle format | what | by | license | comment | |
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| Apr 19, 2016 at 14:16 | comment | added | Peter Green | "Of course it is theoretically possible to multiply by 63 and then divide by 44. But this requires a very fast PLL oscillator for 630 MHz and also a fast frequency divider." It's more than theoretically possible to do this in a single PLL stage. For example the IDT versaclock 5 has a VCO frequency range of 2500 MHz to 2900 MHz. So you could multiply by 252 and divide by 176 | |
| S Apr 19, 2016 at 11:08 | history | suggested | Uwe | CC BY-SA 3.0 |
change the order of multiplication and division
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| Apr 19, 2016 at 10:14 | review | Suggested edits | |||
| S Apr 19, 2016 at 11:08 | |||||
| Apr 19, 2016 at 9:48 | comment | added | pipe | Why are you giving two answers? And why would an Australian need an American color burst frequency? :) | |
| Apr 19, 2016 at 8:14 | comment | added | Tom Carpenter | Or just multiply by 63 and divide by 44. | |
| Apr 19, 2016 at 7:26 | comment | added | Rev | My head spins... | |
| Apr 19, 2016 at 7:03 | review | First posts | |||
| Apr 19, 2016 at 7:10 | |||||
| Apr 19, 2016 at 7:00 | history | answered | Uwe | CC BY-SA 3.0 |