You need paths for bias currents on U1 and U4- a resistor to virtual ground will do.
The resistor value should be low enough that it does not cause too much offset. Also consider the rolloff frequency with the coupling capacitors.
Any realistic simulation should have shown the op-amps gradually drifting towards one the rails, and the initial bias condition should have shown this if you used SPICE, even for a JFET-input op-amp.