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May 14, 2016 at 19:50 comment added Chris Steinbeck Bell You're right, after further investigation i found that my pspice software had not modeled the chip i was using. I had to try it on the breadboard and use the advice you mentioned. Thanks for clarifying your diagram. i can't use the up arrow on your comment, but your response is the one that helped me the most.
May 3, 2016 at 9:49 history edited JIm Dearden CC BY-SA 3.0
Updated diagram to allow for pulsed input
May 3, 2016 at 9:45 comment added JIm Dearden @ChrisSteinbeckBell Either the P-Spice model does not model this chip or you are using a narrow pulse to control the Set or Reset so when it returns to LOW the 1Hz pulse starts again. I've edited the diagram to show a bit of glue logic to allow the use of narrow pulses to control the S-R inputs.
May 2, 2016 at 19:47 comment added Chris Steinbeck Bell I tried this circuit on PSPICE but it didn't worked as i expected. The output keeps the pulse at 1 hz and is not a straight +5dc line. What am i doing wrong?.
May 2, 2016 at 13:31 comment added JIm Dearden Yes. The values of R and C give a time constant which controls the delay after the edges of the incoming pulse. The values you choose will determine the actual width of pulse at the XNOR gate output. With the values given this will be about 7 - 10uS. The JK flip flop converts the two short pulses back to the original 1Hz pulse. Both the Set and Reset are normally held LOW with 10k resistors. With no 'interrupt' or 'setting the output low' the Q output will be the 1Hz pulse. Keeping the Reset High will put (and keep) the Q output Low (no pulse). Keeping the Set High does the opposite.
Apr 30, 2016 at 23:53 comment added Chris Steinbeck Bell Do we mean t=RC right?. So if R and S are "grounded" by a 10k resistor, does this means the output at Q would be a straight pulse?. Sorry but i got lost during the paragraph after recombining the two pulses.
Apr 29, 2016 at 10:01 history answered JIm Dearden CC BY-SA 3.0