Timeline for Is SPI significantly faster than bit-banging?
Current License: CC BY-SA 3.0
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| Nov 19, 2022 at 23:12 | comment | added | 比尔盖子 | Success. Now I've reached 4 cycles/bit. My new procedure: at initialization, load a bitmask to W, load the byte to common RAM, select the port's bank. To transmit a bit, ANDWF the port register and W, so both clocks and data are set to LOW simultaneously. Then test bit, and either skip it or set data to HIGH, finally set clock to HIGH. Thanks for the tip, it's now as fast as it can be. | |
| Nov 18, 2022 at 21:41 | comment | added | supercat | On most PICs, I would generally use the five-cycle approach you describe. There are two ways of improving it to four in some situations: (1) either compute a byte whose bits indicate that a bit differs from the previous one, and then use either "btfsc flipBits,_ / btf DATA_PIN," or "btrsc flipBits, / xorwf DATA_PORT,f" [with W holding the proper bit mask]. Alternatively, one might be able to shave off a cycle by using either IORWF or ANDWF to simultaneously preset the data pin to a known state and set the clock to idle. | |
| Nov 18, 2022 at 21:24 | comment | added | 比尔盖子 | Hi. Do you have any tutorial on high-speed bitbanging in PIC assembly? I'm trying to optimize my PIC program, after some head-scraching, I've reached the speed of 5 cycles/bit (set data to HIGH, test bit and set data to LOW, otherwise skip it, set clock to LOW, set clock to HIGH). But it would be interesting to see how someone else might've done it differently. I'm also curious about the 4 cycles/bit solution on the PICF18. | |
| Dec 7, 2011 at 20:35 | history | answered | supercat | CC BY-SA 3.0 |