Timeline for VHDL if generate in the preamble, is it possible?
Current License: CC BY-SA 3.0
3 events
| when toggle format | what | by | license | comment | |
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| Jun 2, 2016 at 10:11 | comment | added | user8469759 | Never used block statements before, I'm having a look. About the observation, it was just a minimal example it's not an actual design. | |
| Jun 2, 2016 at 10:05 | history | edited | user16324 | CC BY-SA 3.0 |
added 265 characters in body
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| Jun 2, 2016 at 9:58 | history | answered | user16324 | CC BY-SA 3.0 |