Timeline for Nios II system generated by Qsys looks awful (All pin are at one side). Can we make it look better?
Current License: CC BY-SA 3.0
4 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jun 20, 2016 at 0:11 | answer | added | Yossiri | timeline score: 1 | |
| Jun 19, 2016 at 14:49 | comment | added | Tom Carpenter | Though if you ask me, if you want to make it look nicer, instantiate it in a Verilog file not a schematic. | |
| Jun 19, 2016 at 14:48 | comment | added | Tom Carpenter | Nope. Or at least, not in a way that isn't overwritten each time you regenerate it. | |
| Jun 19, 2016 at 7:01 | history | asked | Yossiri | CC BY-SA 3.0 |