Timeline for Quartus 2 VHDL Clock Frequency Divider: can't determine definition of operator "+"
Current License: CC BY-SA 3.0
5 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Jun 23, 2016 at 13:03 | comment | added | Simon Richter |
In VHDL, you can limit allowed values using the range keyword. If you limit to 0 to 3, you would get the desired behaviour, but also an error in simulation because you assign the value 4 for a short time, even if you immediately overwrite it later (because <= assignments are not performed until the end of the block).
|
|
| Jun 22, 2016 at 20:39 | comment | added | Deniz Yildirim | well, I defined count4 and count8 as integers and now the code is working perfectly, but the thing is, compiler uses two 32 bits numbers when a single bit and two bits are necessary for count4 and count8 respectively. Isnt it a waste of memory or will it reduce the number of bits used in the optimization ? | |
| Jun 22, 2016 at 20:35 | comment | added | Simon Richter | My initial guess is that they are trying to be "helpful". | |
| Jun 22, 2016 at 20:29 | comment | added | Deniz Yildirim | But why it makes sense in ISE, but not Quartus ? I used my code in school in ISE 10.1 and it worked, in quartus 2 it did not. | |
| Jun 22, 2016 at 20:03 | history | answered | Simon Richter | CC BY-SA 3.0 |