Timeline for How do you design a CMOS buffer with exact same delay of a CMOS inverter?
Current License: CC BY-SA 3.0
3 events
| when toggle format | what | by | license | comment | |
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| Jul 23, 2016 at 18:25 | comment | added | user16324 | NAND is usually faster than AND, whose implementation is usually a NAND followed by an inverter. | |
| Jul 23, 2016 at 13:43 | comment | added | Jules | I think your first sentence may be the best suggestion here. E.g. if the signal is generated by an AND gate, you could replicate it with a NAND gate tied to the same inputs and that should (AFAICS) have the same propogation delay. | |
| Jul 6, 2016 at 13:05 | history | answered | user16324 | CC BY-SA 3.0 |