Timeline for Unclocked, edge-triggered version of RS flip-flop?
Current License: CC BY-SA 3.0
12 events
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| Jul 13, 2016 at 13:36 | comment | added | jbord39 | A single D-flip flop, particularly the one he has there (I am guessing sn74hc74) is built from 3 inverters, 1 buffer, 4 transmittion gates, and 4 nand gates (30 FET's). So the whole circuit is 30*2 + 8 = 68 FET's. The solution I posted has 6 inverters, 2 and gates, and 2 nor gates = 12 + 12 + 8 = 32 FET's. This is half the devices and if sized appropriately about half the power. The delay of an SR latch is also less than a DFF. I work mostly on low power high speed datapaths so maybe those are not considerations that are important for all. | |
| Jul 13, 2016 at 13:29 | comment | added | Dave Tweed | So now your solution is essentially identical to the one posted by supercat almost 3 years ago. The only difference is that he uses feedback from the output of the SR latch to insure that the pulses at the outputs of his edge detectors are long enough to guarantee correct operation. Your strings of inverters offer no such guarantee. | |
| Jul 13, 2016 at 13:18 | history | edited | jbord39 | CC BY-SA 3.0 |
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| Jul 13, 2016 at 13:16 | comment | added | jbord39 | Ah yes it is silly but we are getting closer? Thank you for the input, I have included another edit with just the rising edge detectors into the SR. This, though, requires that the pulses do not rise too closely in time to each other; or there is an invalid state. This minimum width is set by the width of the edge detectors. | |
| Jul 13, 2016 at 13:05 | comment | added | Dave Tweed | This is getting silly. If you have edge detectors, why do you need the J-K logic at all? Just apply the outputs of the edge detectors directly to the R-S inputs. In fact, the circuit you show will fail if either input is held high and the other one is repeatedly pulsed -- the output will toggle on each pulse rather than remaining in the correct state. | |
| Jul 13, 2016 at 13:05 | history | edited | jbord39 | CC BY-SA 3.0 |
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| Jul 13, 2016 at 12:59 | comment | added | jbord39 | Thank you for the correction. I have modified the circuit to operate as intended. | |
| Jul 13, 2016 at 12:54 | history | edited | jbord39 | CC BY-SA 3.0 |
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| Jul 13, 2016 at 11:11 | comment | added | Dave Tweed | Your description of what happens in a JK latch when both inputs are high is incorrect. The output does not just change state once -- instead, it oscillates freely at a rate determined by the gate delays.This is not what the OP is looking for. | |
| Jul 13, 2016 at 1:50 | history | edited | jbord39 | CC BY-SA 3.0 |
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| Jul 13, 2016 at 1:38 | history | edited | jbord39 | CC BY-SA 3.0 |
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| Jul 13, 2016 at 1:24 | history | answered | jbord39 | CC BY-SA 3.0 |