Timeline for Interfacing memory to papilio fpga board
Current License: CC BY-SA 3.0
6 events
| when toggle format | what | by | license | comment | |
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| Apr 13, 2017 at 12:33 | history | edited | CommunityBot |
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| Jun 7, 2013 at 10:30 | answer | added | FarhadA | timeline score: 1 | |
| Mar 8, 2012 at 23:45 | comment | added | davidd | If you are making a breakout board for it you might as well go ahead and make it a wing for the Papilio expansion ports. Be relatively careful in your routing and you should be able to get 10-50MHz. | |
| Jan 24, 2012 at 11:36 | comment | added | John Burton | Maybe I need to be more specific... If I have a ram chip connected to an fpga by plug in leads, 18 address wires, 8 data wires and 2 control wires, what is a reasonal frequency I could expect it to work at... 100kz? 1MHz, 10Mhz, 50Mhz? Just looking for what is worth trying really. | |
| Jan 22, 2012 at 8:28 | history | tweeted | twitter.com/#!/StackElectronix/status/161002386532483072 | ||
| Jan 21, 2012 at 14:33 | history | asked | John Burton | CC BY-SA 3.0 |