Timeline for How can I turn a clock signal into a logic high that also goes low when the clock drops out?
Current License: CC BY-SA 3.0
7 events
| when toggle format | what | by | license | comment | |
|---|---|---|---|---|---|
| Aug 29, 2016 at 0:28 | vote | accept | Daniel | ||
| Aug 29, 2016 at 0:12 | comment | added | Scott Seidman | You need a retriggerable one shot | |
| Aug 28, 2016 at 23:53 | comment | added | Bruce Abbott | What do you mean by 'differential' clock signal, and how does it get 'sent to ground'? | |
| Aug 28, 2016 at 22:52 | answer | added | jbord39 | timeline score: 2 | |
| Aug 28, 2016 at 22:38 | comment | added | gbulmer | Is the differential clock already clean digital signals? The first part of the problem might be as simple as putting the signals into an exclusive-or, XOR, gate. Then continuously trigger something to hold the output signal across clock transitions. So you need to answer Transistors questions to get complete answers. | |
| Aug 28, 2016 at 22:23 | comment | added | Transistor | You need to specify the frequency, the time-out, what happens if clock freezes high and what happens if it freezes low. | |
| Aug 28, 2016 at 22:10 | history | asked | Daniel | CC BY-SA 3.0 |